1. Field of the Invention
The present invention generally relates to transmission error checking, and more particularly to transmission error checking in result forwarding.
2. Description of the Related Art
CMOS processors of coming generations will have operating frequencies in a range of 5–10 GHz and very small device and wiring geometries on the order of 0.05 μm features. As a result, individual latches and dynamic logic nodes are susceptible to alpha and cosmic ray events. Further, signals are generated by dynamic logics and have pulse rise times of less than or equal to 10 ps along 0.05 μm spaced wires. As a result, transmission errors are likely to occur in the logics. These errors may grow at one order of magnitude per CMOS generation. Thus, transmission error checking is needed on the entire processor core data flow logic.
Parity checking is one of the transmission error checking methods in digital circuits. In computer terminology, parity checking refers to a technique of checking whether data has been lost or changed when it is transmitted from one place to another. An additional binary bit, the parity bit, is added to a group of bits that are transmitted together. This parity bit is used only for the purpose of identifying whether the bits being transmitted arrived successfully. Before the bits are sent, they are added together with no regard to carry (exclusive-OR operation) to generate a source parity bit (parity bit at source). As a result, if the source parity bit is a one, the number of ones among the bits is odd. If the source parity bit is a zero, the number of ones among the bits is even. At the receiving end, the bits being transmitted are again added together with no regard to carry to generate a destination parity bit (parity bit at destination). The destination parity bit is then compared with the source parity bit. If they are the same, it is assumed that the transmission is without error. If they are different, it is assumed that the transmission is with error.
In result forwarding, results of a current cycle at the outputs of a function unit (ALU, rotator, etc.) are forwarded immediately to the function unit's own inputs and to the inputs of other function units for use in a next cycle instead of being first bussed to a common register file and then read from the common register file to the inputs of the function units several cycles later. Most prior art function units do not have any transmission error checking scheme for the result forwarding. Some prior art transmission error checking schemes use full redundant function units or even entire redundant processor cores for error checking.
Accordingly, there is a need for an apparatus and method in which parity checking can be performed for data transmission in result forwarding, without redundant function units or processor cores.